1. Field of the Invention
The present invention relates generally to the field of phase-locked loop (PLL) electronic circuits, and more particularly to an improved switch timing of a charge pump for use in a phase-locked loop circuit.
2. Description of the Related Art
Fully integrated phase-locked loop (PLL) circuits have been widely used in areas such as communications, wireless systems, digital circuits, and disk drive electronics. The operation of conventional charge pump-based phase locked loop circuits are well known in the art. For example, U.S. Pat. No. 6,147,561 describes the operation of the basic block diagram shown in FIG. 1. As described therein, the phase locked loop circuit includes a phase/frequency detector (PFD) 14, a charge pump 18, a loop filter 20, a voltage-controlled oscillator (VCO) 22, a reference divider 12 and an M divider 24.
The basic PLL circuit of FIG. 1 receives an input reference clock signal 10, in form of square waves with reference frequency fref, from a reference frequency source, not shown, usually a crystal oscillator which generates a low jitter or low phase noise reference signal at a known frequency. The reference divider 12 divides the input signal 10 reference frequency fref by an integer R, to allow use of a higher frequency reference source.
The phase/frequency detector 14 has two input terminals, the reference input and the feedback input. The output signal 13 of the reference divider 12 is provided as the reference input signal of the phase/frequency detector 14. The PLL circuit output signal 16 with frequency fout, which is the output of the VCO 22, is divided by the M divider 24. The output signal 25 of the M divider 24 is provided as the feedback input signal into the phase/frequency detector 14.
The phase/frequency detector 14 outputs an UP signal 19 and a DOWN signal 15. When the phase of the reference input signal 13 leads the feedback input signal 25, the phase/frequency detector 14 outputs longer UP pulses and shorter DOWN pulses. When the phase of the feedback input signal 25 leads the reference input 13, the phase/frequency detector 14 outputs longer DOWN pulses and shorter UP pulses. The duration difference of UP and DOWN pulses equals the phase difference of the reference input signal and the feedback input signal.
The charge pump 18 is an analog circuit controlled by the phase/frequency detector outputs, that is, the UP signal 19 and DOWN signal 15, which acts in response to an indication of a phase difference between signals supplied by the reference frequency source and signals supplied by the voltage controlled oscillator 22. The charge pump 18 generates phase error correction current pulses supplied to the loop filter 20 based on the UP/DOWN pulses provided by the phase/frequency detector, in order to pull the input voltage of the voltage controlled oscillator 22 up or down to adjust the frequency of the VCO output signal 16. Conventional charge pump circuits typically contain a current source and a current sink to pull the charge pump 18 output voltage up or down, respectively, by providing appropriate current to a capacitive input of the loop filter 20.
The loop filter 20 smoothes the phase/frequency detector 14 output voltage and determines the loop performance, based upon selected loop filter 20 elements. The output of the loop filter 20 adjusts the input voltage of the voltage-controlled oscillator (VCO) 22 and determines the frequency fout of the output signal 16 of the VCO 22 and the PLL circuit. The output signal 16 of the VCO 22 is then fed back, divided by integer M in the M divider 24, and input into the feedback input of the phase/frequency detector 14.
The PLL circuit produces an output signal 16 whose frequency fout is equal to the value [(fref/R)*M], and the phase of the VCO output signal 16 follows the phase of the input reference signal 10. Therefore, the feedback of the PLL provides a means for locking the phase and frequency fout of the output signal 16 in accordance with the phase and frequency of the input reference signal 10. If the input reference signal 10 has a highly stable reference frequency, the PLL circuit produces the output signal 16 with a highly stable frequency f.out.
Conventional charge pump circuits, however, produce switching transients in the output current pulse signal, which adversely affects the PLL circuit performance. It would be desirable to reduce these switching transients.
In general, the present invention is an improved switching procedure for the current steering type charge pump circuit. A current steering type charge pump circuit according to an embodiment of the present invention includes four control signals, UP, UPB, DN and DNB. In order to produce an UP current pulse output signal, the UPB control signal is first asserted (turned xe2x80x9conxe2x80x9d), followed by the UP control signal. After a period of time, which is proportional to the error signal that needs to be applied to a VCO, the UPB signal is first unasserted (turned xe2x80x9coffxe2x80x9d), followed by the UP signal. This procedure isolates the output during the switching time, and thereby reduces the transients and ripples on the output current signal.
Similarly, to produce a DOWN current pulse output signal (i.e. a xe2x80x9csinkxe2x80x9d current pulse), a DN control is first asserted, followed by a DNB control signal. After a period of time, which is proportional to the error signal that needs to be applied to a VCO, the DN signal is first unasserted (turned xe2x80x9coffxe2x80x9d), followed by the DNB signal.